i.MX35 e-boot splash

這個 driver 是別人從 i.MX31 IPU driver 中的 SDC.C 裡改出來的, 我再給它改成 i.MX35 使用, main function 是 OALDisplaySplashScreen().

改到 i.MX35要更動的東西, 我現在只剩下記得:

1.DISP3 pin (DISP0~2 是 ADC 用的非 SDC 用的).

2.CCM 中 IPU clock 對應的啟動 bits 要打開, i.MX35 上是 CCM[1] bit 18,19.

3.DMA address, i.MX35 我把它指到 image_cfg.h 中 IPU_PA_START, i.MX31 跟 i.MX35 的 frame buffer 地點似乎都不一樣, 寫圖片載入器時記得加載到 OALPAtoUA(IMAGE_BOOT_DISPLAY_RAM_START) 去.

這裡預設的圖片格式是 RGB565 而非 windows 的 ARGB1555, 寫轉換程式時要梢加注意.

兩個要自行 implement.

1.LCD power GPIO pin, 這個要記得給它 enable 而且打開.

2.圖片載入. 這個可能從外面讀進來, 可能從 image 裡解壓縮出來, 不一定, 看使用者高興.

檔案下載:

https://skydrive.live.com/?cid=ea95177ed13eeda8&sc=documents&uc=1&id=EA95177ED13EEDA8%21342#

source code:

#pragma warning(disable: 4100 4115 4201 4204 4214 4702)

#include

#include

#include "loader.h"

// Defines

#define FLOW_ARM 0

#define SDC_DMA_CHANNEL IPU_DMA_CHA_DMASDC_0_LSH // background

//#define SDC_DMA_CHANNEL IPU_DMA_CHA_DMASDC_1_LSH // background

// #define IMAGE_BOOT_DISPLAY_RAM_START IMAGE_WINCE_IPU_RAM_PA_START

// #define IMAGE_BOOT_DISPLAY_RAM_SIZE IMAGE_WINCE_IPU_RAM_SIZE

BOOL OALDisplaySplashScreen(void);

void DumpIMA(PCSP_IPU_REGS pIPU, int ch);

// i.MX35 Registers

static PCSP_CCM_REGS g_pCCM = 0;

static PCSP_IOMUX_REGS g_pIOMUX = 0;

static PCSP_IPU_REGS g_pIPU = 0;

extern BOOL NANDLoadLogoPicture(VOID);

// Init the IPU DMA module

static void SetupIDMAC(int width, int height, int bpp, int nFlip, const int channel)

{ //setup IDMAC Channel Parameter Memory.

UINT32 bpp_code, npb_code, sat_code, bam_code, ofs[4], wid[4];

//=================================

// Configure First 132 bit word

//=================================

// Default access type to 32-bit

sat_code = 2;

bam_code = nFlip ? 1 : 0;

npb_code = 0;

switch (bpp)

{

case 32:

bpp_code = 0;

npb_code = 8 - 1;

ofs[0] = 0;

ofs[1] = 8;

ofs[2] = 16;

ofs[3] = 24;

wid[0] = 8 - 1;

wid[1] = 8 - 1;

wid[2] = 8 - 1;

wid[3] = 8 - 1;

break;

case 24:

bpp_code = 1;

npb_code = 10 - 1;

sat_code = 0;

ofs[0] = 0;

ofs[1] = 8;

ofs[2] = 16;

ofs[3] = 0;

wid[0] = 8 - 1;

wid[1] = 8 - 1;

wid[2] = 8 - 1;

wid[3] = 0;

break;

case 16:

bpp_code = 2;

npb_code = 16 - 1;

ofs[0] = 0;

ofs[1] = 5;

ofs[2] = 11;

ofs[3] = 0;

wid[0] = 5 - 1;

wid[1] = 6 - 1;

wid[2] = 5 - 1;

wid[3] = 0;

break;

case 8:

bpp_code = 3;

npb_code = 32 - 1;

ofs[0] = 0;

ofs[1] = 0;

ofs[2] = 0;

ofs[3] = 0;

wid[0] = 8 - 1;

wid[1] = 0;

wid[2] = 0;

wid[3] = 0;

break;

case 4:

bpp_code = 4;

npb_code = 32 - 1;

ofs[0] = 0;

ofs[1] = 0;

ofs[2] = 0;

ofs[3] = 0;

wid[0] = 4 - 1;

wid[1] = 0;

wid[2] = 0;

wid[3] = 0;

break;

case 1:

bpp_code = 5;

npb_code = 64 - 1;

ofs[0] = 0;

ofs[1] = 0;

ofs[2] = 0;

ofs[3] = 0;

wid[0] = 1 - 1;

wid[1] = 0;

wid[2] = 0;

wid[3] = 0;

break;

default:

bpp_code = 7;

// TODO: Should report error here. bpp_code is reserved.

break;

}

// Set IPU_IMA_ADDR (IPU Internal Memory Access Address)

OUTREG32(&g_pIPU->IPU_IMA_ADDR,

CSP_BITFVAL( IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_CPM) |

CSP_BITFVAL( IPU_IPU_IMA_ADDR_ROW_NU, (2 * channel )) | // channel is 14

CSP_BITFVAL( IPU_IPU_IMA_ADDR_WORD_NU, 0));

//...0th 32 bit word

// XV [9:0], YV [19:10], XB [31:20]

OUTREG32(&g_pIPU->IPU_IMA_DATA,

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_XV, 0) | // 0

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_YV, 0) | // 10

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_XB, 0)); // 20

//...1st 32 bit word

// YB [11:0], SCE [12], RESERVED [13], NSB [14], LNPB [20:15], SX [30:21],

// SY~ [31]

// - Set NSB

OUTREG32(&g_pIPU->IPU_IMA_DATA,

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_YB, 0) | // 32-32

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SCE, 0) | // 44-32

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_NSB, 1) | // 46-32

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_LNPB, 0) | // 47-32

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SX, 0) | // 53-32

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_LOW_SY, 0)); // 63-32

//...2nd 32 bit word

// ~SY [8:0], NS [18:9], SM [28:10] SDX~ [31:29]

OUTREG32(&g_pIPU->IPU_IMA_DATA,

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_HIGH_SY, 0) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_NS, 0) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SM, 0) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_LOW_SDX, 0));

//...3rd 32 bit word

// ~SDX [1:0], SDY [6:2], SDRX [7], SDRY [8], SCRQ [9], RESERVED [11:10]

// - FW [23:12], FH~ [31:24]

// - Set FW & FH

OUTREG32(&g_pIPU->IPU_IMA_DATA,

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_HIGH_SDX, 0) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SDY, 0) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SDRX, 0) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SDRY, 0) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SCRQ, 0) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_FW, (width - 1)) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_LOW_FH, (height - 1)));

//...4th 32 bit word

// ~FH [3:0]

// NOTE: this takes care of the upper four bits in the FH field

OUTREG32(&g_pIPU->IPU_IMA_DATA, ((height - 1) >> 8));

//=================================

// Configure Second 132 bit word

//=================================

if(channel == IPU_DMA_CHA_DMASDC_0_LSH || channel == IPU_DMA_CHA_DMASDC_1_LSH)

{

// Set IPU IPU_IMA_ADDR (IPU Internal Memory Access Address)

// MEM_NU = 0x0001 (CPM)

// ROW_NU = 2*N + 1 (N is channel number)

// WORD_NU = 0

OALMSG(1, (TEXT("SDC DMA addr 0x%08x\r\n"), IMAGE_BOOT_DISPLAY_RAM_START));

OUTREG32(&g_pIPU->IPU_IMA_ADDR,

CSP_BITFVAL( IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_CPM) |

CSP_BITFVAL( IPU_IPU_IMA_ADDR_ROW_NU, (2 * channel + 1)) |

CSP_BITFVAL( IPU_IPU_IMA_ADDR_WORD_NU, 0));

//...parameters for YUV/RGB interleaved - 2nd 132 bit word

//...0th 32 bit word

// EBA0 [31:0], double buffer page 0

// Set buffer #1 to physical frame buffer address

// 在這裡設定 double buffer page 0 起始位置, 必需是絕對位址.

OUTREG32(&g_pIPU->IPU_IMA_DATA, IMAGE_BOOT_DISPLAY_RAM_START);

//...1st 32 bit word

// EBA1 [31:0], double buffer page 1

OUTREG32(&g_pIPU->IPU_IMA_DATA, 0);

}

else

{

//..skip over EBA0 and EBA1 for the viewfinder mode

//.. Set IPU_IMA_ADDR (IPU Internal Memory Access Address)

//EBA0 與 EBA1 不設定, ADDR_WORD_NU = 2 表從第二個 dword 開始設定.

OUTREG32(&g_pIPU->IPU_IMA_ADDR,

CSP_BITFVAL( IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_CPM) |

CSP_BITFVAL( IPU_IPU_IMA_ADDR_ROW_NU, (2 * channel + 1)) |

CSP_BITFVAL( IPU_IPU_IMA_ADDR_WORD_NU, 2));

}

//...2nd 32 bit word

// - BPP [2:0], SL [16:3], PFS [19:17], BAM [24:20], NPB [30:25],

// - RESERVED [31]

// - Set BPP to 24bpp (1)

// - Set SL (Scaling Factor) to bytes_pp * width

// - Set PFS (Packing) to RGB (%100)

OUTREG32(&g_pIPU->IPU_IMA_DATA,

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_BPP, bpp_code) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SL, ((width * bpp / 8) - 1)) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_PFS, 0x4) | //0x4 是 RGB

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_BAM, bam_code) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_NPB, npb_code));

//...3rd 32 bit word

// SAT [1:0], SCC [2], OFS0 [7:3], 0FS1 [12:8], OFS2 [17:13], OFS3 [22:18]

// - WID0 [25:23], WID1 [28:26], WID2 [31:29]

OUTREG32(&g_pIPU->IPU_IMA_DATA,

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SAT, sat_code) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SCC, 0) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS0, ofs[0]) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS1, ofs[1]) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS2, ofs[2]) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS3, ofs[3]) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_WID0, wid[0]) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_WID1, wid[1]) |

CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_WID2, wid[2]));

//...4th 32 bit word

// WID3 [2:0], DEC_SEL [3],

// Set WID3 (7 - 8 bit size), Color component 3 width (Alpha)

OUTREG32(&g_pIPU->IPU_IMA_DATA,

CSP_BITFVAL(IPU_IPU_IMA_DATA_PARAM_WID3, wid[3]));

}

static void EnableSDC2(void)

{

g_pIOMUX = (PCSP_IOMUX_REGS)OALPAtoUA(CSP_BASE_REG_PA_IOMUXC);

g_pIPU = (PCSP_IPU_REGS)OALPAtoUA(CSP_BASE_REG_PA_IPU);

g_pCCM = (PCSP_CCM_REGS)OALPAtoUA(CSP_BASE_REG_PA_CCM);

// Configure IOMUX to request IPU SDC pins

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD0, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD1, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD2, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD3, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD4, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD5, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD6, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD7, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD8, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD9, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD10, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD11, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD12, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD13, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD14, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD15, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD16, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD17, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD18, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD19, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD20, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD21, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD22, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_LD23, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_D3_VSYNC, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_D3_HSYNC, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_D3_FPSHIFT, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_D3_DRDY, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_D3_REV, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);//

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_D3_CLS, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);//

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_D3_SPL, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);//

OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_CONTRAST, DDK_IOMUX_PIN_MUXMODE_ALT0, DDK_IOMUX_PIN_SION_REGULAR);

// Enable DI and SDC

SETREG32(&g_pIPU->IPU_CONF,

CSP_BITFVAL( IPU_IPU_CONF_DI_EN, IPU_IPU_CONF_DI_EN_ENABLE) |

CSP_BITFVAL( IPU_IPU_CONF_SDC_EN, IPU_IPU_CONF_SDC_EN_ENABLE));

// Enable DMA SDC Channel 0

INSREG32BF(&g_pIPU->IDMAC_CHA_EN,

IPU_DMA_CHA_DMASDC_0, IPU_ENABLE);

// Enable SDC background

// Set BG_EN = 1 (Background is enabled)

INSREG32BF(&g_pIPU->SDC_COM_CONF,

IPU_SDC_COM_CONF_BG_EN, IPU_ENABLE);

// Set DMA SDC Channel 0 as ready

INSREG32BF(&g_pIPU->IPU_CHA_BUF0_RDY,

IPU_DMA_CHA_DMASDC_0, IPU_DMA_CHA_READY);

}

static void InitializeSDC2(void)

{

UINT32 g_IPUCLK = 0x7ed6b40;

UINT32 m_PixelClock = 0, m_PixelDivider;

INT WIDTH = 320; //以下參數比照 driver 中 sdc.c 的修改值.

INT HEIGHT = 240;

INT VSYNCWIDTH = 1;

INT VSTARTWIDTH = 17;

INT VENDWIDTH = 4;

INT HSYNCWIDTH = 1;

INT HSTARTWIDTH = 67;

INT HENDWIDTH = 20;

// map registers

g_pIOMUX = (PCSP_IOMUX_REGS)OALPAtoUA(CSP_BASE_REG_PA_IOMUXC);

g_pIPU = (PCSP_IPU_REGS)OALPAtoUA(CSP_BASE_REG_PA_IPU);

g_pCCM = (PCSP_CCM_REGS)OALPAtoUA(CSP_BASE_REG_PA_CCM);

// Enable clock to IPU -- bits 18-19 of CGR1

// Read in current value, "or" it with bits 22-23, write the value back to the register

OUTREG32( &g_pCCM->CGR[1], INREG32(&g_pCCM->CGR[1]) | 0xc0000 );

//----- General configuration

//step 1

// Set little endian

INSREG32BF(&g_pIPU->IPU_CONF, IPU_IPU_CONF_PXL_ENDIAN, IPU_LITTLE_ENDIAN);

//----- Display interface configuration

//step 2

//... SDC_COM_CONF

OUTREG32( &g_pIPU->SDC_COM_CONF,

//.. SDC mode, TFT color

CSP_BITFVAL(IPU_SDC_COM_CONF_SDC_MODE, IPU_SDC_MODE_TFT_COLOR) |

//.. sharp pannel enable

CSP_BITFVAL(IPU_SDC_COM_CONF_SHARP, 0x0) |

//.. dual mode disable, only smart lcd supports dual mode

CSP_BITFVAL(IPU_SDC_COM_CONF_DUAL_MODE, 0));

//step 3, setup panel

//... SDC_HOR_CONF

OUTREG32( &g_pIPU->SDC_HOR_CONF,

//.. display width for tearing and Vsync calculation

// Screen width minus 1. Specifies the number of pixel clock periods between

// the last HSYNC and the new HSYNC.

CSP_BITFVAL(IPU_SDC_HOR_CONF_SCREEN_WIDTH, (WIDTH + HSTARTWIDTH + HENDWIDTH )) | //nathan

//.. horizontal synchronization pulse, actually hsync pulse width is 1

CSP_BITFVAL(IPU_SDC_HOR_CONF_H_SYNC_WIDTH, HSYNCWIDTH - 1));

//... SDC_VER_CONF

OUTREG32( &g_pIPU->SDC_VER_CONF,

//..line/pixel resolution

CSP_BITFVAL(IPU_SDC_VER_CONF_V_SYNC_WIDTH_L, 0x1) |

//..display height for tearing and Vsync calculation

CSP_BITFVAL(IPU_SDC_VER_CONF_SCREEN_HEIGHT, (HEIGHT + VSTARTWIDTH + VENDWIDTH)) | //nathan

//..vsync size, vsync width is 1

CSP_BITFVAL(IPU_SDC_VER_CONF_V_SYNC_WIDTH, VSYNCWIDTH));

//step 4

OUTREG32(&g_pIPU->DI_DISP_IF_CONF,

//..data mask for display 3

CSP_BITFVAL( IPU_DI_DISP_IF_CONF_DISP3_DATAMSK, 0x0) | //0

// select interface display clock for display 3

CSP_BITFVAL( IPU_DI_DISP_IF_CONF_DISP3_CLK_SEL, 0) |

// display clock idle enable

CSP_BITFVAL( IPU_DI_DISP_IF_CONF_DISP3_CLK_IDLE, 0)); // 0x1

OUTREG32(&g_pIPU->DI_DISP_SIG_POL,

//..1: inverse data polarity

CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_DATA_POL, 0) |

//..display interface clock polarity

CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_CLK_POL, 0) |

//..1: active high horizontal signal polarity

CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_HSYNC_POL, 1) |

//..1: active high vertical signal polarity

CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_VSYNC_POL, 1) |

// output enable polarity

CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_DRDY_SHARP_POL, 1));

//step 5

// HSP_CLK = 133 MHz

//

// DI_CLK = HSP_CLK * HSP_CLOCK_PER = 133 MHz

// ==> HSP_CLOCK_PER = 1

// these are 7 bit fields iiiffff

// where i = integer part and f = fractional part of the value

OUTREG32(&g_pIPU->DI_HSP_CLK_PER,

CSP_BITFVAL( IPU_DI_HSP_CLK_PER_HSP_CLK_PERIOD_1, 1 << 4) |

CSP_BITFVAL( IPU_DI_HSP_CLK_PER_HSP_CLK_PERIOD_2, 1 << 4));

m_PixelClock = ( WIDTH + HSTARTWIDTH + HSYNCWIDTH + HENDWIDTH) * ( HEIGHT + VSTARTWIDTH + VSYNCWIDTH + VENDWIDTH) * 60;

g_IPUCLK = 0x7ed6b40;

m_PixelDivider = (g_IPUCLK << 4) / m_PixelClock; // g_IPUClk is 0x3F6B5A0

if (m_PixelDivider < 0x40) // Divider less than 4

{

DEBUGMSG(SDC_ERROR,

(TEXT("InitPanel() - Pixel clock divider less than 1\r\n")));

m_PixelDivider = 0x40;

}

OUTREG32(&g_pIPU->DI_DISP3_TIME_CONF,

//..write strobe end

CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_DOWN_WR, (m_PixelDivider / 8) - 1) |

//.. period

CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_PER_WR, m_PixelDivider));

//step 6

//... DI_DISP_ACC_CC

INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,

// Display clock cycles number minus 1 for output/input one data word. This

// bit describe in which clock displayed bit is masked.

IPU_DI_DISP_ACC_CC_DISP3_IF_CLK_CNT_D, 0);

//step 7

//... DI_DISP3_B0_MAP

OUTREG32(&g_pIPU->DI_DISP3_B0_MAP,

// set0; data offset

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS0, 0x5) |

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS1, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS2, 0) |

// set0; data maping

// mask LSB

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M0, 3) |

// mask LSB

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M1, 3) |

// Enable LSB in the first clock cycle

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M2, 0) |

// enable LSB in the first clock cycle

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M3, 0) |

// enable LSB in the first clock cycle

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M4, 0) |

// enable LSB in the first clock cycle

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M5, 0) |

// enable LSB in the first clock cycle

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M6, 0) |

// enable LSB in the first clock cycle

CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M7, 0));

//... DI_DISP3_B1_MAP

OUTREG32(&g_pIPU->DI_DISP3_B1_MAP,

// set1; data offset

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS0, 0xb) |

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS1, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS2, 0) |

// set1; data maping

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M0, 3) |

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M1, 3) |

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M2, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M3, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M4, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M5, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M6, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M7, 0));

//... DI_DISP3_B2_MAP

OUTREG32(&g_pIPU->DI_DISP3_B2_MAP,

// set2; data offset

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS0, 0x11) |

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS1, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS2, 0) |

// set2; data maping

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M0, 3) |

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M1, 3) |

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M2, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M3, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M4, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M5, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M6, 0) |

CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M7, 0));

//step 8

//----- SDC Configuration

//Select graphic window to be on foreground or background.

// background selected

INSREG32BF(&g_pIPU->SDC_COM_CONF,

IPU_SDC_COM_CONF_GWSEL, IPU_SDC_COM_CONF_GWSEL_BG);

// Graphic window alpha mode. Select the use of alpha to be global or local.

// global alpha selcted

// INSREG32BF(&g_pIPU->SDC_COM_CONF,

// IPU_SDC_COM_CONF_SDC_GLB_LOC_A, 1);

//disable alpha channel, 這部份是參考 u-boot 2011.09 的版本.

OUTREG32(&g_pIPU->SDC_GRAPH_WIND_CTRL, INREG32(&g_pIPU->SDC_GRAPH_WIND_CTRL) & 0x00ffffffL);

{

UINT32 reg;

reg = INREG32(&g_pIPU->SDC_COM_CONF);

//Graphic window alpha mode is global (1).

reg |= 0x40L;

//Graphic window select. Graphic window is background (0).

reg &= ~0x20L;

//Graphic window color keying enable, Disable color keying of graphic window (0)

reg &= ~0x80L;

OUTREG32(&g_pIPU->SDC_COM_CONF, reg);

}

OUTREG32(&g_pIPU->SDC_BG_POS,

CSP_BITFVAL( IPU_SDC_BG_POS_BGXP, HSTARTWIDTH) | //nathan

CSP_BITFVAL( IPU_SDC_BG_POS_BGYP, VSTARTWIDTH)); //nathan

OUTREG32(&g_pIPU->SDC_FG_POS,

CSP_BITFVAL( IPU_SDC_FG_POS_FGXP, HSTARTWIDTH+1) | //nathan

CSP_BITFVAL( IPU_SDC_FG_POS_FGYP, VSTARTWIDTH)); //nathan

//step 9

//----- IDMAC Configuration

// Set no double-buffer, use single buffer

INSREG32BF(&g_pIPU->IPU_CHA_DB_MODE_SEL, IPU_DMA_CHA_DMASDC_0, IPU_SIG_BUF); //14

INSREG32BF(&g_pIPU->IPU_CHA_DB_MODE_SEL, IPU_DMA_CHA_DMASDC_1, IPU_SIG_BUF); //15

// Set buffer 0 as current buffer (non double buffered)

// for chanel DMASDC_0, current buffer is buffer 0

INSREG32BF(&g_pIPU->IPU_CHA_CUR_BUF, IPU_DMA_CHA_DMASDC_0, IPU_SIG_BUF);

// for chanel DMASDC_1, current buffer is buffer 0 too.

INSREG32BF(&g_pIPU->IPU_CHA_CUR_BUF, IPU_DMA_CHA_DMASDC_1, IPU_SIG_BUF);

// Set high priority for DMA SDC Channel 0

INSREG32BF(&g_pIPU->IDMAC_CHA_PRI,

IPU_DMA_CHA_DMASDC_0, 1);

// Set high priority for DMA SDC Channel 1

INSREG32BF(&g_pIPU->IDMAC_CHA_PRI,

IPU_DMA_CHA_DMASDC_1, 1); //original is 1.

// Set high priority for DMA SDC Channel 1

// INSREG32BF(&g_pIPU->IDMAC_CHA_PRI,

// IPU_DMA_CHA_DMASDC_3, 1);

// Set max for consecutive bursts for each channel

INSREG32BF(&g_pIPU->IDMAC_CONF,

IPU_IDMAC_CONF_SRCNT, 7);

// Select source of SDC channel as ARM

// SDC background channel 0 source select as MCU(arm).

// SDC foreground channel 1 source select as MCU(arm).

OUTREG32(&g_pIPU->IPU_FS_DISP_FLOW,

CSP_BITFVAL( IPU_IPU_FS_DISP_FLOW_SDC0_SRC_SEL, FLOW_ARM) |

CSP_BITFVAL( IPU_IPU_FS_DISP_FLOW_SDC1_SRC_SEL, FLOW_ARM));

// Turn contrast fully on

OUTREG32(&g_pIPU->SDC_CUR_BLINK_PWM_CTRL,

// Source select. Selects the input clock source for the PWM counter. The

// PWM output frequency is equal to the frequency of the input clock divided by 256.

// source select as pixel clock

CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_SCR, 1) |

// Contrast control is on.

CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_CC_EN, 1) |

//

CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_PWM, 0xffL));

SetupIDMAC(320, 240, 16, FALSE, IPU_DMA_CHA_DMASDC_0_LSH); // SDC_DMA_CHANNEL is 14

}

BOOL OALDisplaySplashScreen(void)

{

InitializeSDC2();

//NANDLoadLogoPicture();

EnableSDC2();

OALMSG(1, (TEXT("-DisplaySplashScreen(%d)\r\n"), success));

return TRUE;

}